It is often important to the proper operation of many circuits that the various parts of the overall circuit are synchronized. This is especially true of high speed circuits, which often have critical timing requirements. In order to accomplish synchronization, clock signals are propagated throughout the circuit. Without compensation, significant skew may be introduced into the clock signal due to propagation delay, thereby adversely affecting the performance of the circuit. This skew can be quite significant when all parts of the circuit are not on the same component, and may even be significant when all parts of the circuit are on the same chip in high speed applications. A significant source of skew is in the system clock tree in which a variety of clock signals of varying frequencies and duty cycles are generated based directly or indirectly on a reference clock.
In order to compensate for this skew, some conventional circuits intentionally introduce delay into the reference clock signal prior to the reference clock signal being provided to a system clock tree. The intentionally introduced delay, when added to the delay introduced by the clock tree results in the reference clock signal after being propagated through the system clock tree to be approximately in phase with the reference clock signal prior to the introduction of the intentional delay.
One way of intentionally producing this delay is to pass the reference clock signal through a delay line having an adjustable number of delay elements, each introducing a relatively fixed amount of delay to the reference clock. The number of delay elements through which the reference clock passes is then adjusted until a phase detector detects that the phase of the reference clock signal after the system clock tree is appropriately equal to the phase of the reference clock signal provided to the phase detector. A delay line and phase detector in this configuration are referred to as a delay locked loop since the configuration is able to generate a signal having a relatively fixed (or locked) amount of delay with respect to a reference clock signal.
While this method is useful for providing a derived clock signal that is in phase with a reference clock signal (albeit with one or more cycles of delay) while accounting for system clock tree skew, the method does not allow for quadrature or other clock signals having a fixed angle of delay to be generated while compensating for system clock tree skew. The method has no mechanism for calculating a clock cycle in terms of delay elements. Accordingly, the method does not facilitate the generation of a quadrature or other clock signal having a fixed angle of delay to be generated while at the same time compensating for system clock tree skew.
There are also conventional circuits that generate a quadrature clock signal or a clock signal with some fixed angle of delay based on a reference signal. Such circuits accomplish this by using a delay line having an adjustable number of delay elements. The number of delay elements are adjusted until the phase of the reference clock signal at the output terminal of the delay line is approximately the same as (but with one or more cycles of delay) the phase of the reference clock signal provided to the input terminal of the phase detector. Based on the number of delay elements needed to accomplish this, the number of delay elements that are needed to generate a fixed angle of delay is then calculated. The reference signal is then provided to another delay line and passed through that calculated number of delay elements to generate the delayed clock signal that is derived from the reference clock signal. While such circuits allow for the generation of a derived clock signal having a fixed angle of delay with respect to the reference clock signal, the period of delay introduced into the derived clock signal is independent of system clock tree skew introduced into the path of the derived clock signal having the fixed angle of delay.
Accordingly, what would be advantageous is a delay locked loop circuit that generates a clock signal that has a fixed angle of delay with respect to a reference clock signal while at the same time accounting for system clock delay. It would further be advantageous if the delay locked loop circuit reaches an accurate locked state quickly to thereby increase the proportion of time that the delay locked loop circuit is locked and therefore accurately generating a phase delayed signal, and thereby shortening system initialization time. What would further be advantageous is a delay locked loop circuit in which jitter is reduced. Jitter is a common problem in delay locked loop circuit and refers to the frequent and extensive change in phase difference between the derived clock signal and the reference clock signal. Larger jitter profiles tend to reduce system performance and reduced ability to run at higher frequencies due to the correspondingly reduced timing margins between multiple system devices.